Sram cell with asymmetrical transistors for reduced leakage

ABSTRACT

A method of fabricating an SRAM cell with reduced leakage is disclosed. The method comprises fabricating asymmetrical transistors in the SRAM cell. The transistors are asymmetrical in a manner that reduces the drain leakage current of the transistors. The fabrication of asymmetrical pass transistors comprises forming a dielectric region on a surface of a substrate having a first conductivity type. A gate region having a length and a width is formed on the dielectric region. Source and drain extension regions having a second conductivity type are formed in the substrate on opposite sides of the gate region. A first pocket impurity region having a first concentration and the first conductivity type is formed adjacent the source. A second pocket impurity region having a second concentration and the first conductivity type may be formed adjacent the drain. If formed, the second concentration is smaller than the first concentration, reducing the gate induced drain leakage current.

FIELD OF THE INVENTION

This invention generally relates to electronic circuits, and morespecifically to fabrication and structure of field-effect transistorswith asymmetrical threshold voltages.

BACKGROUND OF THE INVENTION

The continuing popularity of portable electronic devices presentsmanufacturers with significant challenges. Increasing capability ofelectronic devices is moderated by considerations of cost, size, weight,and battery life. These considerations have increasingly resulted inhigher levels of semiconductor integration. Thus, portable electronicdevices frequently embed memory, control, signal processors, and othercircuit functions on a single integrated circuit. Further optimizationof these portable electronic devices dictates even greater reduction ingeometric feature sizes and spaces between these geometric features.Shrinking feature sizes require lower supply voltages to limit maximumelectric fields. Transistor leakage must be minimized to reduce standbycurrent and prolong battery life. Even with lower supply voltages,however, special considerations are required for reliable deviceoperation.

One problem of source/drain resistance was addressed by Yamazaki, U.S.Pat. No. 5,547,888, which is incorporated herein by reference in itsentirety. Therein, Yamazaki discloses a disadvantage of symmetricallightly doped drain (LDD) transistors in a static random access memory(SRAM) cell. Yamazaki discloses that hot carrier reliability onlydepends on the drain structure and not the source structure. Yamazakialso discloses that a source LDD region may limit on current of thetransistor and require a greater channel length. Yamazaki discloses amethod of masking the source region of the transistor during the LDDimplant to produce an asymmetrical transistor with only a drain LDDimplant.

A problem of punch through with short channel lengths was addressed byWang et al., U.S. Pat. No. 6,566,204, which is incorporated herein byreference in its entirety. Punch through occurs when source and draindepletion regions of a field effect transistor extend across thechannel. Under these conditions, the overlying control gate can nolonger control current flow between the source and drain. Pocketimplants were previously used to locally increase bulk concentration inthe channel region of the field effect transistor, thereby limitingdepletion region width and resulting punch through. Pocket implants inthe drain region, however, limited drive current and increased thresholdvoltage. Wang et al. disclosed that punch through could be effectivelycurtailed with an asymmetrical pocket implant adjacent the source of thefield effect transistor. Wang et al. further disclose a method ofblocking the pocket implant at the drain of the field effect transistorwith a mask pattern in close proximity to the control gate of the fieldeffect transistor. The close proximity of the mask pattern selectivelyblocks the angled pocket implant but permits implantation ofsource/drain zones without the need for additional masking steps.

Lien, U.S. Pat. No. 5,790,452, is incorporated herein by reference inits entirety. Lien applied an angled pocket implant to a static randomaccess memory (SRAM) cell to solve a different problem. Referring toFIG. 1A, there is a schematic diagram of an SRAM cell 100 of the priorart disclosed by Lien as FIG. 2. The SRAM cell includes a latch formedby load resistors 101 and 102 and N-channel drive transistors 103 and104. The latch is connected between positive supply voltage Vdd 112 andground or Vss 114. The supply voltage levels Vdd and Vss are alsoreferred to as high and low levels, respectively, for simplicity.Storage nodes 116 and 118 of the latch are connected to bitlines 108 and110 by access transistors 105 and 106, respectively.

Lien disclosed two conflicting modes of operation of the SRAM cell.During write-disturb mode the SRAM cell of FIG. 1A is not accessed andthe wordline 120 is low. Storage nodes 116 and 118 are low and high,respectively, and complementary bitline 110 is low. Under thiscondition, access transistor 106 has significant subthreshold leakage.Lien discloses a high threshold voltage, therefore, is desirable tolimit subthreshold leakage when storage node 118 is high and bitline 110is low. During read mode bitlines 108 and 110 are both initially highand wordline 120 is high. When the latch storage nodes 116 and 118 arelow and high, respectively, Lien discloses an advantage to a lowthreshold voltage on access transistor 106. This low threshold voltageof access transistor 106 provides a higher voltage at storage node 118and, therefore, a greater gate voltage at drive transistor 103. Thus,Lien discloses an advantage of a low threshold voltage of accesstransistor 106 when bitline 110 is positive with respect to storage node118 in read mode.

Referring to FIG. 1B, there is a cross section of N-channel accesstransistor 106 of the prior art as disclosed by Lien at FIG. 3. Theaccess transistor 106 includes N+ source/drain region 118 connected tostorage node 118 and N+ source/drain region 110 connected to bitline110. An N-type lightly doped region 132 extends from N+ source/drainregion 118 into the channel region under control gate 134. A P-typepocket implant encloses N+ source/drain region 110. When the N+ drain118 is positive with respect to N+ source 110, Lien discloses accesstransistor 106 has a high threshold voltage. Alternatively, when the N+drain 110 is positive with respect to N+ source 118, access transistor106 has a low threshold voltage.

SUMMARY OF THE INVENTION

In accordance with a preferred embodiment of the invention, there isdisclosed a method fabricating an SRAM cell with reduced leakage. Themethod comprises fabricating asymmetrical transistors in the SRAM cell.The transistors are asymmetrical in a manner that reduces the gateinduced drain leakage current of the transistors. The fabrication ofasymmetrical pass transistors comprises forming a dielectric region on asurface of a substrate having a first conductivity type. A gate regionhaving a length and a width is formed on the dielectric region. Sourceand drain extension regions having a second conductivity type are formedin the substrate on opposite sides of the gate region. A first pocketimpurity region having a first concentration and the first conductivitytype is formed adjacent the source. A second pocket impurity regionhaving a second concentration and the first conductivity type may beformed adjacent the drain. If formed, the second concentration issmaller than the first concentration, reducing the gate induced drainleakage current.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing features of the present invention may be more fullyunderstood from the following detailed description, read in conjunctionwith the accompanying drawings, wherein:

FIG. 1A is a diagram of a static random access memory (SRAM) cell of theprior art;

FIG. 1B is a cross sectional view of prior art access transistor 106 ofFIG. 1A;

FIG. 2 is a schematic diagram of a six-transistor static random accessmemory cell that may advantageously use the present invention;

FIG. 3 is a layout diagram of an array of four memory cells as in FIG.2;

FIG. 4A is a layout diagram of the array of four memory cells of FIG. 2with an P-channel implant mask;

FIG. 4B is the layout diagram of FIG. 4A showing the outline of theimplant mask for clarity;

FIG. 5A is cross section of a P-channel transistor showing a pocketimplant of the present invention;

FIG. 5B is a drain-to-source surface concentration profile of thetransistor of FIG. 5A;

FIG. 6 is another embodiment of the layout diagram of FIG. 4B;

FIG. 7 is yet another embodiment of the layout diagram of FIG. 4B;

FIG. 8A is a layout diagram of a memory cell as in FIG. 2 in horizontalorientation showing the effect of implant azimuth angles on P-channelload transistors;

FIG. 8B is a layout diagram of a memory cell as in FIG. 2 in verticalorientation showing the effect of implant azimuth angles on P-channelload transistors;

FIG. 9A is a layout diagram of a transistor in horizontal orientationshowing the effect of implant azimuth angles rotated by 45 degrees withrespect to FIG. 10A;

FIG. 9B is a layout diagram of a transistor in vertical orientationshowing the effect of implant azimuth angles rotated by 45 degrees withrespect to FIG. 10A;

FIG. 10A is an exemplary cross section diagram showing the effect ofimplant tilt angle for an edge of a single transistor;

FIG. 10B is an exemplary cross section diagram showing the effect ofimplant tilt angle for edges of adjacent transistors;

FIG. 11 is a graph showing minimum tilt implant angle required to blocka pocket implant as a function photoresist thickness and space from agate edge with 25 nm misalignment;

FIG. 12 is a graph showing minimum tilt implant angle required to blocka pocket implant as a function photoresist thickness and space from agate edge with 30 nm misalignment;

FIG. 13 is a graph showing minimum tilt implant angle required to blocka pocket implant as a function photoresist thickness and space from agate edge with 35 nm misalignment;

FIG. 14 is a graph showing the minimum LDD clearance for various resistCD's, gate-to-gate opening spaces, and overlay specifications; and

FIG. 15 is a block diagram of a wireless telephone as an example of aportable electronic device which could advantageously employ the presentinvention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Referring to FIG. 15, there is a block diagram of a wireless telephoneas an example of a portable electronic device which could advantageouslyemploy this invention. The wireless telephone includes antenna 1700,radio frequency transceiver 1702, baseband circuits 1710, microphone1706, speaker 1708, keypad 1720, and display 1722. The wirelesstelephone is preferably powered by a rechargeable battery (not shown) asis well known in the art. Antenna 1700 permits the wireless telephone tointeract with the radio frequency environment for wireless telephony ina manner known in the art. Radio frequency transceiver 1702 bothtransmits and receives radio frequency signals via antenna 1702. Thetransmitted signals are modulated by the voice/data output signalsreceived from baseband circuits 1710. The received signals aredemodulated and supplied to baseband circuits 1710 as voice/data inputsignals. An analog section 1704 includes an analog to digital converter1724 connected to microphone 1706 to receive analog voice signals. Theanalog to digital converter 1724 converts these analog voice signals todigital data and applies them to digital signal processor 1716. Analogsection 1704 also includes a digital to analog converter 1726 connectedto speaker 1708. Speaker 1708 provides the voice output to the user.Digital section 1710 is embodied in one or more integrated circuits andincludes a microcontroller unit 1718, a digital signal processor 1716,nonvolatile memory circuit 1712, and volatile memory circuit 1714.Nonvolatile memory circuit 1712 may include read only memory (ROM),ferroelectric memory (FeRAM), FLASH memory, or other nonvolatile memoryas known in the art. Volatile memory circuit 1714 may include dynamicrandom access memory (DRAM), static random access memory (SRAM), orother volatile memory circuits as known in the art. Microcontroller unit1718 interacts with keypad 1720 to receive telephone number inputs andcontrol inputs from the user. Microcontroller unit 1718 supplies thedrive function to display 1722 to display numbers dialed, the currentstate of the telephone such as battery life remaining, and receivedalphanumeric messages. Digital signal processor 1716 provides real timesignal processing for transmit encoding, receive decoding, errordetection and correction, echo cancellation, voice band filtering, etc.Both microcontroller unit 1718 and digital signal processor 1716interface with nonvolatile memory circuit 1712 for program instructionsand user profile data. Microcontroller unit 1718 and digital signalprocessor 1716 also interface with volatile memory circuit 1714 forsignal processing, voice recognition processing, and other applications.

Turning now to FIG. 2, the electrical circuit corresponding to exemplarymemory cell 300 of FIG. 3 will be explained in detail. Each of the fourmemory cells 300-306 of FIG. 3 is electrically identical to theschematic diagram of FIG. 2. Moreover, the geometric layout of eachmemory cell of FIG. 3 is substantially identical except that they may beplaced in different views. Memory cell 300 is bounded to the right andbelow by memory cells 304 and 302, respectively, as indicated by thesolid line cell boundaries. Memory cell 300 includes a latch formed byP-channel load transistors 201 and 202 and N-channel transistors 203 and204. These transistors are indicated by polycrystalline silicon gateregions crossing an active region. Source terminals of P-channel loadtransistors 201 and 202 are connected to positive Vdd supply voltage inmetal (not shown) at metal-to-P+ contact areas 212. Drain terminals ofload transistors 201 and 202 are connected to the storage nodes 216 and218. Likewise, source terminals of N-channel driver transistors 203 and204 are connected to ground or Vss supply voltage in metal (not shown)at metal-to-N+ contact areas 214. Drain terminals of the N-channeldriver transistors 203 and 204 are connected to the storage nodes 216and 218 in metal (not shown). Each of the metal-to-silicon contact areas212 and 214 is formed by a half contact in each of two adjacent cells.Storage nodes 216 and 218 are output terminals of the latch as indicatedat FIG. 3 by metal-to-P+ contact areas. The connection of the drain oftransistor 203 and drain of transistor 201 comprising storage node 216is not shown for clarity. Similarly, the connection of the drain oftransistor 204 and drain of transistor 202 comprising storage node 218is not shown. These storage nodes 216 and 218 are connected to accessN-channel transistors 205 and 206, respectively. Gates of the N-channeltransistors 205 and 206 are connected to word line 220 indicated by adashed line. The other terminals of N-channel transistors 205 and 206are connected to bit line BL_(A) 208 and complementary bit line /BL_(A)210 indicated by dotted lines, respectively.

Decreasing feature sizes and gate oxide thicknesses of present processtechnology make the memory cell of FIGS. 2 and 3 particularlysusceptible to off-state drain leakage current, which includes both gateinduced drain leakage (GIDL) and gate-edge diode drain leakage (GEDL).This problem occurs, for example, when storage nodes 216 and 218 arehigh and low, respectively. P-channel load transistor 201 is on andN-channel driver transistor 203 is off. Complementary P-channel loadtransistor 202, therefore, is off and N-channel driver transistor 204 ison. N-channel drive transistor 203 has a high level (Vdd) at the drainor storage node 216 and ground at the source terminal 214. The gate ofN-channel transistor 203 is held low by N-channel transistor 204. Thislow level of the gate holds the channel region adjacent the drain ofN-channel transistor 203 in strong accumulation. This creates a highelectric field at the lightly doped drain junction (LDD) and the P-typechannel under the gate edge. The electric field is particularly highwhen the substrate adjacent the drain is fabricated with a P+ pocketimplant. The resulting high electric field may even deplete or invertthe N-type drain LDD region. This creates a gate induced drain leakage(GIDL) current path even when N-channel transistor 203 is off. Likewise,the diode formed between the LDD region and the substrate exhibits aleakage current (GEDL). This leakage current also increases withincreasing P+ pocket region concentration.

A corresponding gate induced drain leakage current path may exist inP-channel load transistor 202. P-channel load transistor 202 has a highlevel (Vdd) at the source and a low level at the drain or storage node218. The gate of P-channel transistor 202 is held high by P-channeltransistor 201. This high level of the gate holds the channel regionadjacent the drain of P-channel transistor 202 in strong accumulation.This creates a high electric field at the lightly doped drain junction(LDD) and the N-type substrate under the gate edge. This high electricfield may even deplete or invert the P-type drain LDD region. Theelectric field is particularly high when the substrate adjacent thedrain is fabricated with an N+ pocket implant. The resulting highelectric field creates a gate induced drain leakage (GIDL) current patheven when P-channel transistor 202 is off. Likewise, the diode formedbetween the LDD region and the substrate exhibits a leakage current(GEDL). This leakage current also increases with increasing N+ pocketregion concentration.

These drain leakage current paths may exist in N-channel drivetransistors, P-channel load transistors, or both. The cumulative leakagecurrent for a typical memory array significantly increases standbycurrent. Elimination of the pocket implant improves the drain leakagecurrent path but introduces new problems of low threshold voltages andeven punch through. Thus, an asymmetrical pocket implant adjacent thesource and blocked from the drain provides a solution to the drainleakage current that does not introduce other problems. It is alsodesirable to avoid introduction of an additional mask step to form thisasymmetrical pocket implant while maintaining an existing lightly dopeddrain (LDD) implant as will be described in detail.

Turning now to FIG. 4A, there is a layout diagram of the array of fourmemory cells of FIG. 2 with a P-channel implant mask formed byphotoresist. The mask includes portions 400, 401, and 402, which coverN-channel transistors 203, 204, 205 and 206, and portions 404, 405, 406,and 407, formed between adjacent P-channel load transistors. FIG. 4B isthe layout diagram of FIG. 4A showing the outline of the implant maskunder the cell geometries for clarity. Mask portion 404 is adjacent andspaced apart from load transistor gate edges 409 and 410, respectively.The space between each mask portion and the respective adjacent gateedge allows a lightly doped P-type ion implant with a small tilt angleto produce lightly doped source and drain regions on each loadtransistor. The closely spaced photoresist portion 404 blocks drain-sideload transistor gate edges 409 and 410 from receiving angled N-typepocket implants as will be explained in detail. The pocket implant isnot blocked from source-side load transistor gate edges 411 and 412.Thus, the asymmetrical N-type pocket implant and the lightly dopedsource and drain implants may be performed without an extra photoresistmask step according to the embodiment of FIG. 4B.

Referring now to FIG. 5A, there is a cross section diagram showing anexemplary P-channel load transistor such as transistors 201 and 202according to the present invention. FIG. 5B is a corresponding surfaceconcentration extending from source region 904 to drain region 912 ofthe P-channel load transistor of FIG. 5A. The P-channel load transistoris fabricated on an N-well region or substrate formed on a P-substrate.A gate dielectric 916 is formed over the N-well substrate. A controlgate 900 is formed over the gate dielectric 916. P+ source 904 and drain912 regions are formed on each side of the control gate 900.Corresponding P-type LDD regions 906 and 910 are formed adjacentrespective P+ regions 905 and 912 to complete the source and drainregions. An N-type impurity pocket implant is formed adjacent the sourceregion 906. The N-type impurity pocket implant, however, is at leastpartially blocked adjacent the drain region 910. Referring to FIG. 5B,therefore, the concentration of pocket implant 908 adjacent sourceregion 906 has a greater concentration than the portion adjacent drainregion 910. This asymmetrical P-channel load transistor advantageouslyreduces gate induced drain leakage current in the memory array withrespect to memory cells with drain pocket implants. The source pocketimplant maintains an acceptable threshold voltage and avoids punchthrough at normal operating voltages. Moreover, a single mask step isused to form the asymmetrical pocket implant and the symmetrical LDDimplant.

Turning now to FIG. 6, there is another embodiment of the layout diagramof FIG. 4B. The widths of photoresist mask portions 600, 602, 604, and606 have been increased relative to FIG. 4B. Thus, load transistor edges409 and 410 are coincident with the edges of the photoresist portion600. The photoresist mask portions 600, 6002, 604, and 606 may even beenlarged further such that they overlap the load transistor gateregions. This embodiment completely blocks an N-type pocket implant fromthe bitline terminal side of a load transistor at edges 409 and 410while permitting the implant at the opposite edges. However, due to theabsence of any clearance between the resist edge and the gate edge, ifthis photoresist mask is used for the lightly doped source and drainextension implants, the lightly doped extension implants will also beblocked. As a result, this embodiment requires that the pocket implantbe performed with the photoresist mask of FIG. 6, and the light dopedsource and drain extension implants be performed with anotherphotoresist mask wherein portions 600, 602, 604, and 606 are eithernarrow as in FIG. 4B or not present at all. This embodiment may beadvantageously used in a fabrication process where a threshold voltageadjust photoresist mask that is not common to the light doped source anddrain implant is available. This, the asymmetrical N-type pocket implantmay be performed using the threshold voltage adjust mask and without anextra photoresist mask step.

FIG. 7 is yet another embodiment of the layout diagram of FIG. 4B. Thewidths of photoresist mask portions 700, 702, 704, and 706 have beendecreased relative to FIG. 4B. This decrease in photoresist mask widthprovides greater space between the load transistor edges 409 and 410 andthe photoresist mask region 700. This embodiment advantageously producesa larger clearance for the lightly doped source and drain extensionimplants to enter the substrate adjacent both sides of the accesstransistor gate. The narrow photoresist mask regions are limited bymanufacturing capability. However, relatively narrower photoresist maskregions such as region 700 are possible when connected to widerphotoresist mask regions such as region 708. Thus, the asymmetricalN-type pocket implant and the lightly doped source and drain implantsmay be performed without an extra photoresist mask step according to thepresent embodiment.

Turning now to FIG. 8A, there is a layout diagram of a memory cell as inFIG. 2 in horizontal orientation showing the effect of implant azimuthangles on P-channel load transistors 1000 and 1002. P-channel loadtransistor 1000 is adjacent photoresist mask edge 1001. P-channel loadtransistor 1002 is adjacent photoresist mask edge 1003. In oneembodiment of the present invention, pocket implants are applied at fourazimuth angles of 0°, 90°, 180°, and 270°. In this embodiment 90° and270° azimuth pocket implants will enter the substrate on both sides ofthe load transistors 1000 and 1002, and will therefore not create anyasymmetry. The 0° and 180° azimuths create the asymmetry as follows. The0° implant enters the storage node side 201 of the load transistor 1000and is blocked from the drain side 218 of the load transistor 1002.Likewise, the 180° implant enters the source side 202 of the passtransistor 1002 and is blocked from the drain side 216 of the loadtransistor 1000. Thus, both P-channel load transistors 1000 and 1002advantageously receive asymmetrical N-type pocket implants.

This four-azimuth embodiment also creates asymmetrical pass transistorsfor memory cells placed in the orientation shown in FIG. 8B, where the0° and 180° azimuth implants enter both sides of the load transistorsand the 90° and 270° azimuth implants generate the asymmetry. In thisembodiment, the lightly doped source and drain extension implants areapplied either at zero tilt or at a small tilt angle preferably smallerthan 7°, thus entering the substrate on all sides of the loadtransistors. Alternatively, they can be implanted using a separatephotoresist mask as described before. If none of these alternatives isadopted, some asymmetry in lightly doped source and drain extensionswill also occur, which may be acceptable in certain conditions.

In another embodiment of the present invention, pocket implants areapplied at only two azimuth angles. Referring to FIG. 8A, pocketimplants are applied only at the 0° and 180° azimuths. The advantage ofthis embodiment is that greater asymmetry is achieved since the pocketimplants at 90° and 270°, which would enter the substrate on both sidesof the load transistors, are no longer present. If the SRAM cells followthe orientation of FIG. 8B, however, pocket implants must be applied atthe 90° and 270° azimuths. As a result, a possible disadvantage of thisembodiment is that all SRAM cells must be placed in the same orientationon the chip; however, the cell orientation may be restricted for otherreasons, in which case this additional reason for restriction of theorientation would not be a disadvantage. In this embodiment, lightlydoped source and drain extension implants are applied either at zerotilt, or at a small tilt angle preferably smaller than 7°, or applied atany tilt angle at the 90° and 270° azimuths, thus entering the substrateon all sides of the pass transistors. Alternatively, they can beimplanted using a separate photoresist mask as described before.

In another embodiment of the present invention, the pocket implants areapplied at four azimuths of 45°, 135°, 225°, and 315°. Referring now toFIG. 9A, there is a layout diagram of transistor 1100 in horizontalorientation showing the effect of implant azimuth angles rotated by 45degrees with respect to FIG. 8A. For this cell orientation, the gate oftransistor 1100 blocks the N-type pocket implant between the gate andphotoresist mask 1101 for 45° and 315° azimuth angles. Likewise, thephotoresist mask edge 1101 blocks the N-type pocket implant between thegate and photoresist mask 1101 for 135° and 225° azimuth angles. TheNtype pocket implant, however, is applied to the opposite side oftransistor 1100 by 45° and 315° azimuth angles. FIG. 9B is a layoutdiagram of transistor 1102 in vertical orientation showing the effect ofimplant azimuth angles rotated by 45 degrees with respect to FIG. 8A.For the vertical cell orientation, the gate of transistor 1102 blocksthe N-type pocket implant between the gate and photoresist mask 1103 for225° and 315° azimuth angles. Likewise, the photoresist mask edge 1103blocks the N-type pocket implant between the gate and photoresist mask1103 for 45° and 135° azimuth angles. The N-type pocket implant,however, is applied to the opposite side of transistor 1103 by 225° and315° azimuth angles. Thus, a rotation of azimuth implant angles by 45°degrees with respect to FIG. 8A advantageously eliminates cellorientation dependence. In this embodiment, the lightly doped source anddrain extension implants are applied either at zero tilt or at a smalltilt angle preferably smaller than 7°, thus entering the substrate onall sides of the pass transistors. If they are tilted, they can beimplanted at any set of azimuth angles, including 0, 90, 180, and 270,or 45, 135, 225, and 215. Alternatively, they can be implanted using aseparate photoresist mask as described before. If none of thesealternatives is adopted, some asymmetry in lightly doped source anddrain extensions may occur in this case, which may be acceptable incertain conditions.

Referring to FIG. 10A, there is an exemplary cross section diagramshowing the effect of implant tilt angle for an edge of a singletransistor. The transistor includes gate region 1200 formed over gatedielectric 1240. A photoresist mask 1202 is closely spaced from the gateregion 1200 to block an N-type pocket implant in the area there between.An LDD implant, indicated by dashed arrows 1210-1218, is applied withvertical or 0° tilt angle. Alternatively, the LDD implant may be appliedat a substantially vertical tilt angle of preferably less than 7° withthe same result. In this manner, the LDD implant is applied equally toboth source and drain edges of the transistor, as long as there isenough clearance between the gate and the photoresist to allow the LDDimplant to enter the substrate. An N-type pocket implant, indicated bysolid arrows 1220-1230, is applied with tilt angle of plus or minus βwith respect to vertical as shown. In this manner, the N-type pocketimplant 1220-1224 is applied to the left side of the transistor butblocked from the right side by transistor gate 1200. The N-type pocketimplant 1226-1230 is blocked from the right side of the transistor byphotoresist mask 1202.

Referring to FIG. 10B, there is an exemplary cross section diagramshowing the effect of implant tilt angle for edges of adjacenttransistors. The adjacent transistors include gate regions 1200 and 1201each formed over the substrate. A photoresist mask 1202 is spacedbetween the two gates. The photoresist is shown with some misalignmenttoward the gate 1201. Because of this misalignment, relatively lessphotoresist exists to block the N-type pocket implant 1250 compared tothe implant 1252. For a given opening 1262 between the two gates, agiven photoresist CD 1261, a given misalignment or overlay error, and agiven pocket implant tilt angle, there is a minimum photoresist heightthat must exist to ensure successful blocking of both pocket implants1250 and 1252. In those embodiments of the present invention in whichthe LDD implants are not applied with the photoresist mask described inFIG. 4A, 4B, 6, or 7, successful application of the LDD implants not aconsideration in designing the photoresist mask.

FIGS. 11-13 show graphs of the minimum photoresist height required toblock the pocket implant for various misalignment conditions. FIG. 11 isa graph showing minimum photoresist height required to block pocketimplants for a 190 nm opening between the gates and with 35 nmmisalignment. FIG. 12 is a graph showing minimum photoresist heightrequired to block pocket implants for a 190 nm opening between the gatesand with 25 nm misalignment. FIG. 13 is a graph showing minimumphotoresist height required to block the pocket implants for a 220 nmopening between the gates and with 25 nm misalignment.

In those embodiments of the present invention where LDD implants areapplied using the same photoresist mask as the pocket implants, thephotoresist mask must not only block the pocket implants but also permitthe LDD implants to reach the substrate on both source and drain sidesof the gates. Returning to FIG. 10B, because of the misalignment, theclearance for the LDD implant is smaller near the gate 1201 compared tonear the gate 1200. For a given opening between the gates, thephotoresist CD and the misalignment specification must be set such thatthe necessary clearance will depend on process details such as the LDDimplant dose, the amount of diffusion occurring in subsequent thermalsteps, and the design of the heavily doped source and drain regions inany specific manufacturing process. FIG. 14 shows a graph of the LDDimplant clearance as a function of the photoresist CD, the openingbetween the gates, and the overlay specification. For example, with aresist CD of 110 nm, an overlay specification of 25 nm, and a gate togate opening of 220 nm, a satisfactory minimum clearance of 30 nm isobtained.

While this invention has been described with reference to illustrativeembodiments, this description is not intended to be construed in alimiting sense. Various modifications and combinations of theillustrative embodiments, as well as other embodiments of the invention,will be apparent to persons skilled in the art upon reference to thedescription. In view of the foregoing discussion, it is intended thatthe appended claims encompass any such modifications or embodiments.

1-7. (canceled)
 8. An SRAM memory cell, comprising: a storage node; asupply node; and an asymmetrical load transistor connected between thestorage node and the supply node, wherein the asymmetrical loadtransistor has a first drain leakage current when said supply node ispositive with respect to the storage node and said asymmetrical loadtransistor has a second drain leakage current of greater magnitude thanthe first drain leakage current when the supply node is negative withrespect to the storage node.
 9. The SRAM memory cell of claim 8, whereinthe asymmetrical load transistor comprises a more heavily doped pocketimplant region on the supply node side relative to the storage nodeside.
 10. The SRAM memory cell of claim 9, wherein said asymmetricalload transistor comprises a source region and a drain region of a firstconductivity type and wherein said pocket implant region is of a secondconductivity type, opposite said first conductivity type. 11-13.(canceled)
 14. A memory cell; comprising: a first supply voltageterminal; a first storage node; a second supply voltage terminal; asecond storage node; a first transistor having a source and drain andformed on a substrate having a first conductivity type, the firsttransistor having the source coupled to the first supply voltageterminal and the drain coupled to the first storage node; and a secondtransistor having a source and drain and formed on a substrate having asecond conductivity type, the second transistor having the drain coupledto the second storage node and the source coupled to the second supplyvoltage terminal, wherein at least one of the first and secondtransistors has a higher dopant concentration of a respective substrateconductivity type adjacent a respective source than adjacent arespective drain.
 15. The memory cell of claim 14 in which the substrateof the first conductivity type is formed on a substrate of the secondconductivity type.